UCIe Chiplet Controller IP
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9
IP
from 5 vendors
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9)
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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Universal Chiplet Interconnect Express (UCIe 1.0) Controller
- Package Flexibility
- Power Efficiency
- Low Latency
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INNOLINK-C PHY
- LPDDR5 like interface with IO voltage 0.4V and core power supply 0.9V
- 12Gbps for maximum IO speed in HLMC 28nm process
- Default 64-bit DQ Tx+ 64-bit DQ Rx per module, module number can be 1/2/4/8/16 or more
- Burst data, forward clock, no CDR
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UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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16G UCIe Standard PHY for TSMC 7nm
- 16Gbps per pin and supports 12/8/4Gbps subrates
- High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
- BIST features ensure Known Good Die (KGD)
- Sideband for link management and robust training
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16G UCIe Standard PHY for TSMC 3nm
- 16Gbps per pin and supports 12/8/4Gbps subrates
- High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
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16G UCIe Advanced PHY for TSMC 3nm
- 16Gbps per pin and supports 12/8/4Gbps subrates
- High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
- BIST features ensure Known Good Die (KGD)
- Sideband for link management and robust training
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
