TSMC 40ULP IP
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47
IP
from 8 vendors
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10)
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4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
- Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
- High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
- High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.
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1Kx8 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 1.1V / 2.5V CMOS process
- Low voltage: VDD 1.1 V ± 10% read and VDDP 2.1 V ± 5% program
- High speed program: 10-us single-bit programming
- High speed read: 9-MHz read clock at 8-bit word.
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Nano power DC-DC converter in TSMC 40uLP with ultra-low quiescent current and high efficiency at light load
- Low quiescent current suitable for standby modes
- High efficiency at light load extending battery lifetime
- Low ripple level compatible with noise sensitive loads
- Low BoM cost: 1 µH inductor
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DC/DC buck converter in TSMC 40ULP with low quiescent current and high efficiency at light load
- Low quiescent current suitable for standby modes
- High efficiency at light load extending battery lifetime
- Low ripple level compatible with noise sensitive loads
- Low BoM cost: 1 µH inductor
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1Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
- Fully compatible with TSMC 40ULP 1.1/2.5V
- Low voltage: 1.1V+/-10% for read and 2.3V+/-0.1V for program
- High speed: 10us program time up to 4 bits at the same time
- Deep sleep mode to cut down power consumption
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PMK Library IPs at TSMC 40ULP Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
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LPKT Library IPs at TSMC 40ULP Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
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ECO Library IPs at TSMC 40ULP Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
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USB2.0 build-in clock PHY, TSMC 40ULP
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
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USB1.1 FS/LS PHY, TSMC 40ULP
- Smallest USB1.1 PHY IP worldwide with PLL inside (<0.1mm²)
- Fully compliant with Universal Serial Bus (USB) 1.1 electrical specification
- Integrated PLL to provide a variety of stand-alone clock outputs