SSD Controller IP
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20
IP
from 16 vendors
(1
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10)
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PCIe-NVMe SSD Controller Platform
- Compliant to NVMe specification (pass UNH-IOL compliance test)
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High Performance NVMe for PCIe-based storage
- NVM Express Compliant
- Automatic NVMe Command management
- Single I/O queue
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SM4-XTS Crypto Accelerator
- Widebus interface
- Key size: 128 bits
- Key scheduling in hardware
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NAND Flash Controller (NFC) IP for SSD Controller
- Support all kinds of 2D/3D, SLC/MLC/TLC/QLC NAND Flash
- Supports 8KB~32KB NAND page size
- Support 1 to 8 FLASH channels
- Support all Flash command & optional command
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ONFI 5.0 PHY IP
- Compliant with ONFI 5.0 specification
- Supports NV-DDR2 mode
- Supports NV-DDR3, NV-LPDDR4, with a maximum rate of 2400MT/s
- Supports PHY Independent TX/RX Training mode
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High Throughput and Low Latency Compression Engine For SSD
- Implements a LZ77 variant algorithm
- High performance capabilities, meaning the highest compression ratio for a given search buffer size. It delivers 1.5 times more compression compared to the most popular hardware compression algorithm, LZW.
- High throughput of 16Gbps is achieved in ASIC. However, with custom implementations the compression throughput can be as high as 64Gbps.
- Low latency is achieved by designing the engine in two pipe stages. The first pipe stage is referred to as the "Search" pipe in which the search for the longest match string takes place. The second pipe stage is the "Post Processor" used to output unmatched characters and length/offset pairs.
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HBM3 PHY IP at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
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GDDR6 PHY IP for 12nm
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low frequency RDQS mode support
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64-bit embedded processor, fully compliant with the RISC-V ISA
- RV64IAC M + U Modes
- Up to 1.5 GHz in 28nm
- 1.8 DMIPS/MHz
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ONFI Flash Controller
- AXI System Interface
- NAND Flash
