The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. SATA-HC IP block simplifies the integration of high capacity SSDs utilizing SATA I/II/III at 1.5/3/6Gbit/s data rates.The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.The lower protocol layers Phy/Link/Transport are implemented in an all-RTL solution, which minimizes access time by providing the shortest possible path between SSD and application.
SATA HOST Controller
Overview
Key Features
- Designed to SATA v3.0 (6Gbps)
- Low Latency: 66K IOPS Read, 67K IOPS Write (4k blocks)
- Connects to SAPIS compliant serial ATA Phy
- Manage SATA reference frequency difference between the FPGA and the Disk
- AXI Light interface for register access
- AXI Stream Interface and for data transfers
- Power management mode handled by state machine
- Link Layer enable BIST loopback and pattern generation modes
- Transport Layer Support BIST FIS transmission and reception
- Phyical Layer Power management mode handled by state machine
- CONT and data scramblers to reduce EMI
- Auto inserted HOLD primitives
- Supports Gen 1 (1.5 Gbps), Gen 2 (3.0 Gbps) and Gen 3 (6.0 Gbps)
- Small Footprint 5200 LUTs (lower layers)
- PHY/LINK/Trans/App layers in RTL
- DMA management SW in embedded CPU
- CRC generation and checking
- Host operating system not required
- Connects to SAPIS compliant serial ATA Phy
- S.M.A.R.T data collection
- Fault management, BER monitoring
- Detailed traffic analysis & statistics collection
Benefits
- Integrated solution provides the highest possible Megabytes per second.
- AXI Interface
- Compact
- Cost-effective & Flexible
- Many Shipping Products
- Sustained throughput enables consistent and predictable high performance.
Applications
- Trade execution & monitoring
- Data Storage & Capture systems
- HPC / Big Data systems
- Signal processing systems
- Data Mining
Deliverables
- Encrypted compiled netlist
- Datasheet & Documentation
- Simulation Test bench
- Build scripts for ISE/Vivado
- Sample Synthesis scripts
- Support for integration into FPGA
- Reference Resign
- ucLinux Drivers