SRAM-PUF IP
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11
IP
from 6 vendors
(1
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10)
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32-bit SRAM/PROM Controller
- AMBA AHB interface
- Low area consumption
- Compatible with AMBA-2.0
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High-Performance Edge AI Accelerator
- Performance: Up to 16 TOPs
- MACs (8x8): 4K, 8K
- Data Types: 1-bit, INT8, INT16
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Performance Efficiency Leading AI Accelerator for Mobile and Edge Devices
- Performance: Up to 4 TOPs
- MACs (8x8): 512, 1K, 2K
- Data Types: 1-bit, INT8, INT16
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Deeply Embedded AI Accelerator for Microcontrollers and End-Point IoT Devices
- Performance: Up to 1 TOPs
- MACs (8x8): 64, 128, 256, 512
- Data Types: 1-bit, INT8, INT16
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Performance Efficiency AI Accelerator for Mobile and Edge Devices
- Performance: Up to 4 TOPs
- MACs (8x8): 512, 1K, 2K
- Data Types: 1-bit, INT8, INT16
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Performance AI Accelerator for Edge Computing
- Performance: Up to 16 TOPs
- MACs (8x8): 4K, 8K
- Data Types: 1-bit, INT8, INT16
- Internal SRAM: Up to 16 MB
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Lowest Cost and Power AI Accelerator for End Point Devices
- Performance: Up to 512 GOPs
- MACs (8x8): 64, 128, 256
- Data Types: 1-bit, INT8, INT16
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GCRAM, the highest-density on-chip embedded memory in standard CMOS
- High-density bitcell offering up-to 2X area reduction over high-density 6T SRAM.
- Full logic compatibility with standard CMOS, no additional process steps or cost.
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Image Signal Processor (5MP, 2X Sensors) IP
- Self-contained, no external memory needed
- ARM® Cortex-R4 CPU @500 MHz
- Up to 2 Mbytes of SRAM
- Up to 4 Mbytes of stacked Flash or 16 Mbyte external Flash with update via communication interfaces
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I2C Controller IP – Slave, User Register Interface, No CPU Required
- The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host CPU required). The DB-I2C-S-REG processes the I2C protocol & physical layers, and receives & transmits bytes with respect to the I2C payload to / from User Registers or SRAM/FIFO.
- The DB-I2C-S-REG runs off an external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.
