The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host CPU required). The DB-I2C-S-REG processes the I2C protocol & physical layers, and receives & transmits bytes with respect to the I2C payload to / from User Registers or SRAM/FIFO.
The DB-I2C-S-REG runs off an external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.
The DB-I2C-S-REG is a member of Digital Blocks DB-I2C Controller IP Core family, which includes I2C Master/Slave, I2C Master-only, and I2C Slave-only configurations.
Figure 1 depicts the DB-I2C-S-REG Core system view. The IP is configured by internal pre-synthesis parameters and post-synthesis top-level input signals, receives input clock and reset, and performs I2C Slave-Receiver transfers (for loading User Registers) and Slave-Transmitter transfers (for reading User Registers).
