I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

Overview

The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs interfacing to user registers while autonomous in that it does not require a local host CPU for configuration.

The DB-I2C-S-REG runs off an external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.

The DB-I2C-S-REG writes I2C payload bytes into User Registers synchronous to the external clock or reads and transmits User Register data over the I2C bus.

Key Features

I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
Autonomous I2C Slave Controller:

No local CPU host required
No configuring of control/status registers

7- or 10-bit I2C Slave addressing, SCL Low Wait States
Supports five I2C bus speeds:

Standard mode (100 Kb/s)
Fast mode (400 Kb/s)
Fast mode plus (1 Mbit/s)
Ultra fast mode (5 Mbit/s)
Hs-mode (3.4 Mbit/s)

Compliance with I2C specifications:

Philips – The I2C-Bus Specification, Version 2.1, January 2000
NXP Rev .5 October 9, 2012
Fully-synchronous, synthesizable Verilog RTL core. Easy integration into FPGA or ASIC design flows.

Block Diagram

Deliverables

Verilog RTL Source or technology-specific netlist.
Comprehensive testbench suite with expected results.
Synthesis scripts.
Installation & Implementation Guide.
Technical Reference Manual.

Technical Specifications

Foundry, Node

Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC

Maturity

Successful in Customer Implementations

Availability

Immediately

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