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Compare 1,660 IP from 164 vendors (1 - 10)
  • SHA IP Core with native SHA2-256 HMAC support
    • FIPS PUB 180-4 compliant SHA2-256 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224 and 256 bit modes support
    Block Diagram -- SHA IP Core with native SHA2-256 HMAC support
  • 256-bit SHA Secure Hash Crypto Engine
    • The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits.
    • Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics.
    Block Diagram -- 256-bit SHA Secure Hash Crypto Engine
  • SHA 256-bit hash generator
    • Compliant to FIPS 180-2 specification of SHA-256.
    • Internally implemented bit padding unit.
    • Supports input message length multiple of 8-bit.
    Block Diagram -- SHA 256-bit hash generator
  • SHA-256 IP
    • SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles.
    • Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. 
    Block Diagram -- SHA-256 IP
  • Secure Hash Algorithm 256 IP Core
    • FIPS PUB 180-4 compliant SHA2-256 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224 and 256 bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 256 IP Core
  • Secure Hash Algorithm 512 IP Core
    • FIPS PUB 180-4 compliant SHA2-512 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224, 256, 384, 512-bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 512 IP Core
  • Secure Hash Algorithm 384 IP Core
    • FIPS PUB 180-4 compliant SHA2-384 function
    • RFC 2104 compliant HMAC mode native support
    • SHA2 224, 256, 384-bit modes support
    • Secure storage for precomputed HMAC keys
    Block Diagram -- Secure Hash Algorithm 384 IP Core
  • SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
    • Supports variable length SHA-3 Hash Functions
    • Supports Extendable Output Functions (XOF)
    • Configurable architecture for achieving the required performance and silicon area
    Block Diagram -- SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
  • Highest performance Six-wide, out-of-order core with a shared cluster cache enabling up to a 32-core cluster
    • Full support for the RVA22 RISC-V profile specification and Vector 1.0 and Vector Crypto for enabling 64-bit apps processors running feature rich OS stacks such as Linux and Android.
    • Breakthrough RISC-V performance
    • >12 SpecINT2k6/GHz (P870 Processor)
    • P800-Series Architectural Features
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Semiconductor IP