SHA IP
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256-bit SHA Cryptoprocessor Core
- Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
- Implemented according to the IEEE P1619™/D16 standard
- NIST Certified
- Maximum message length up to (264 – 1) bits
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SHA IP Core with native SHA2-256 HMAC support
- FIPS PUB 180-4 compliant SHA2-256 function
- RFC 2104 compliant HMAC mode native support
- SHA2 224 and 256 bit modes support
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SHA 256-bit hash generator
- Compliant to FIPS 180-2 specification of SHA-256.
- Internally implemented bit padding unit.
- Supports input message length multiple of 8-bit.
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AES + SHA DMA Crypto Accelerator
- Control interface
- Crypto Algorithms (AES)
- Hash Algorithms
- DMA Controller
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SHA256 Encoder and Decoder
- FIPS 180-2 compliance
- Message compression
- Key expansion
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SHA1, SHA2 Cryptographic Hash Cores
- Completely self-contained; does not require external memory
- SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2.
- HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input.
- Flow-through design; flexible data bus width
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SHA512 & SHA384 core
- Simple register based interface
- 81 clock cycles per 1024 bits of input data
- AMBA 3 APB slave interface
- DMA flow-control interface
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SHA256 & SHA224 core
- Simple register based interface
- 65 clock cycles per 512 bits of input data
- AMBA 3 APB slave interface
- DMA flow-control interface
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Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
- PUF-based Hardware Root of Trust (Riscure Common Criteria Certified)
- Comprehensive Crypto Engine (NIST CAVP Certified)
- PSA Certified Level 2 Ready
