IP Catalog > RapidIO 3.1

RapidIO 3.1 IP

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  • High Performance DDR5/4/3 Memory Controller
    • Compliant with AXI4 Specification
    • Compliant with DFI 3.1 Specification
    • Compliant with JEDEC DDR3, DDR3L, DDR4 and DDR5 standards
    • Supports 64, 32, 16 and 8 bit Memory SDRAM for DDR3L, DDR4 and DDR5
    Block Diagram -- High Performance DDR5/4/3 Memory Controller
  • Universal Multiport Memory Controller - LPDDR 3/2 Controller
    • Compliant with AXI V4.0 specification
    • Compliant with DFI 3.1 specification
    • Compliant with JEDEC LPDDR2 and LPDDR3 standards
    • Support for 8, 16, 32 SDRAM bus width, for a total memory data path width up to 64 bits
    Block Diagram -- Universal Multiport Memory Controller - LPDDR 3/2 Controller
  • RapidIO EndPoint Controller IP
    • Compliant with RapidIO Interconnect 2.2 specification
    • Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
    • Supports high link utilization and low latency
    • Supports efficient receive and transmit buffering scheme
  • LogiCORE IP Serial RapidIO Gen 2
    • 1x, 2x, & 4x Serial PHY - supports Artix-7, Kintex-7, Zynq-7000, Virtex-7, and Virtex-6 FPGAs
    • 1x, 2x & 4x Serial PHY - supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gbps line speed
    • Supports IDLE1 and IDLE2 sequence
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO LogiCORE IP
    • 1x & 4x Serial PHY - Supports Virtex-6 LXT/SXT/HXT, Spartan-6 LXT, Virtex-5 LXT/SXT/FXT, and Virtex-4 FX FPGAs
    • 1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
    • 1x & 4x Serial PHY - 64-bit internal data path
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO Controller
    • Fully compliant with the RapidIO specification revision 2.2,
    • Simple transaction interface with Host processor and DMA Engine,
    • Configurable FIFOs implemented by BlockRAM in both transmit and receive paths,
    • Register file containing all necessary architectural registers providing total software control of IP core,
  • RapidIO
    • Feature rich
    • Easy to use
    • Robust solution
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