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Compare 63 IP from 19 vendors (1 - 10)
  • RSA Keygen IP Core
    • RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'.
    • This standard specifies methods for generating RSA key pairs.
    • RSA Keygen IP Cores support key pair generation up to 4096 bits.
    Block Diagram -- RSA Keygen IP Core
  • RSA IP Core
    • RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm specifications defined in 'FIPS 186'.
    • This standard specifies methods for digital signature generation and verification using the RSA Digital Signature Algorithm.
    • RSA IP cores support bit lengths from 256 to 4096.
    Block Diagram -- RSA IP Core
  • RSA Signature Verification IP Core
    • Minimal Resource Requirements: The entire XIP5012C requires less than 280 LUTs (lookup tables) and 2 internal memory blocks (Xilinx® Zynq®-7000).
    • Performance: Despite its small size, XIP5012C can support more than 10 digital signature verification operations per second.
    • Standard Compliance: XIP5012C is compliant with FIPS 186-4.
    Block Diagram -- RSA Signature Verification IP Core
  • Block Diagram -- 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
  • Scalable RSA and Elliptic Curve Accelerator
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the interface.
    Block Diagram -- Scalable RSA and Elliptic Curve Accelerator
  • RSA public key cryptography with APB interface
    • For a typical 1024-bit keysize the modular exponentiation can be performed 25 times faster than a pure software implementation. A 1024-bit message can be encrypted (public key of 65537) in 50,000 clock cycles and decrypted in 3,600,000 clock cycles. The peripheral can also be used with software support for CRT based decryption and for generating keys. Using CRT can reduce the cycle count by 1/4.
    • The core is very small; when targeting TSMC90LP at 200MHz it comprises only 17k gates for the logic and an equivalent 32k gates including all memories.
  • RSA Public Key Exponentiation Accelerator
    • Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration)
    • Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
    • Support for RSA binary fields of configurable bit sizes up to 2048
    • Microprocessor-friendly interface
    Block Diagram -- RSA Public Key Exponentiation Accelerator
  • RSA Public Key Cryptography Exponentiation Accelerator
    • Low footprint
    • High throughput
    • 2048-bit length inputs
    • Short exponent lengths
  • RSA2-AHB Accelerator Core with AHB Interface
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the AHB interface.
    Block Diagram -- RSA2-AHB Accelerator Core with AHB Interface
  • RSA/ECC Public Key Accelerators with TRNG and AHB
    • Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
    • Public key signature generation, verification and key negotiation with little involvement of host
    • NIST CAVP compliant for FIPS 140-3
    Block Diagram -- RSA/ECC Public Key Accelerators with TRNG and AHB
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