RSA IP
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Secure-IC Securyzr™ Tunable Cryptography solutions with embedded side-channel protections: AES - SHA2 - SHA3 - PKC - RSA - ECC - Crystals Kyber - Crystals Dilithium - XMSS - LMS - SM2 - SM3 - SM4 - Whirlpool - CHACHA20 - Poly1305
- Tunability for consumer requirements
- Security (different levels, SCA, FIA)
- Modes
- Area
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RSA Signature Verification IP Core
- Minimal Resource Requirements: The entire XIP5012C requires less than 280 LUTs (lookup tables) and 2 internal memory blocks (Xilinx® Zynq®-7000).
- Performance: Despite its small size, XIP5012C can support more than 10 digital signature verification operations per second.
- Standard Compliance: XIP5012C is compliant with FIPS 186-4.
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100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
- For RSA, Diffie-Hellman and ECC
- With AMBA AHB, AXI4 and APB
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Scalable RSA and Elliptic Curve Accelerator
- Small size: RSA5X starts from less than 15K ASIC gates
- Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
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Secure key computation, encryption, decryption, signature and verification functionalities compliant with the PKCS#1
- key generation, encryption, decryption, signature and verification functions
- fully compliant with the PKCS#1 standards
- all key sizes supported up to 8192 bits
- core functions ASM-optimized for the targeted processor
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Secure cryptographic library compliant with the X9.31 and FIPS 186-4 standards.
- fully compliant with the X9.31 and FIPS 186-4 standards (probable primes)
- supported RSA key sizes up to 4096 bits
- unlimited prime generation
- optimized for 32-bit RISC architectures
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Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Direct Memory Access (DMA) and arbiter
- shared memory: no extra silicon cost; inputs and results directly accessible by software
- multiple arithmetic operations: integer multiply, multiply & accumulate, square, addition, subtraction; modular multiplication
- all 32 bits multiple operations up to 8192 bits
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Java Card compliant cryptographic library for encryption and decryption of RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- key generation, encryption, decryption, signature and verification functions
- all key sizes supported up to 8192 bits
- core functions ASM-optimized for the targeted processor
- configurable architecture: adjustable trade-off between performance and RAM footprint; dedicated coprocessor available separately (about 10 times faster)
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RSA public key cryptography with APB interface
- For a typical 1024-bit keysize the modular exponentiation can be performed 25 times faster than a pure software implementation. A 1024-bit message can be encrypted (public key of 65537) in 50,000 clock cycles and decrypted in 3,600,000 clock cycles. The peripheral can also be used with software support for CRT based decryption and for generating keys. Using CRT can reduce the cycle count by 1/4.
- The core is very small; when targeting TSMC90LP at 200MHz it comprises only 17k gates for the logic and an equivalent 32k gates including all memories.
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RSA Public Key Exponentiation Accelerator
- Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration)
- Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
- Support for RSA binary fields of configurable bit sizes up to 2048
- Microprocessor-friendly interface
