PCIe Gen 4 IP
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25
IP
from 10 vendors
(1
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10)
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PCI Express Gen 4 PHY
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
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PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
- Compatible with PCIe base Specification
- Full compatible with PIPE4.2 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
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PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
- Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
- Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
- Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
- Tunable receiver detection to detect worse case cables
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Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane
- TSMC 28HPC process
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High Performance, Low Latency PCIe Gen5 PHY
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
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PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
- Silicon Proven in GF 22GDX with 0.8V and 1.8V power supply.
- Compatible with PCIe base Specification
- Support 32-bit/16-bit parallel interface
- Support for PCIe3(8.0Gbps)
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DO-254 AXI Bridge For PCI Express 1.00a
- Zynq™-7000, Kintex™-7, Virtex™-7, Artix™-7, Virtex™-6 and Spartan®-6 FPGA Integrated Blocks for PCI Express
- Kintex™-7 / Virtex™-7 / Artix™-7 x1, x2, x4, x8 Gen 1 and x1, x2, x4 Gen 2
- Virtex™-6 x1, x2, x4 Gen 1 and x1, x2 Gen 2
- Spartan®-6 x1 Gen 1
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PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- PCie Gen 5/6 compliant
- Up to 112G PAM 4 support
- less than 6 pj/bit typical power consumption