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PCI Express Gen 4 IP

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Compare 24 IP from 13 vendors (1 - 10)
  • PCI Express Gen 4 PHY
    • Support 16GT 8GT 5GT 2.5GT data rate
    • Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
    • x1, x2, x4, x8, x16 lane configuration with bifurcation
    • Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • PCI Express Gen 1/2/3/4 Phy
    • TSMC advanced 16 nm FFC CMOS process
    • Available in 1X, 4X, 8X, and 16X configuration
    Block Diagram -- PCI Express Gen 1/2/3/4 Phy
  • PCI Express Gen 1/2/3/4 Phy
    • 2.5/5.0/8/16 Gbps per lane interface optimized for PCI Express applications
    • Compliance to PCI Express 1.0a, 1.1 and 2.1, 3.1 and 4.0 PIPE specifications
    Block Diagram -- PCI Express Gen 1/2/3/4 Phy
  • PCI Express Gen 1/Gen 2 Phy
    • 2.5/5.0 Gbps per lane interface optimized for PCI Express applications
    • Conforms to PCI Express Specification 1.0a, 1.1 and 2.0
    • PIPE compliant parallel interface
    Block Diagram -- PCI Express Gen 1/Gen 2 Phy
  • PCI Express Verification IP
    • Supports PCI Express specs 1.0/2.0/2.1/3.0/4.0/5.0/6.0
    • Supports mPCIe
    • Supports PIPE, PCS/PMA, Message Bus and SERDES interface
    • Supports MPHY RMMI and serial interface
    Block Diagram -- PCI Express Verification IP
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
  • Multi-Channel Flex DMA IP Core for PCI Express
    • The Multi-Channel DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces.
    • Up to 16 independent AXI Stream Slaves write DMA Data to the Host. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic.
    • Each channel operates on a separate memory area. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.
    Block Diagram -- Multi-Channel Flex DMA IP Core for PCI Express
  • DO-254 AXI Bridge For PCI Express 1.00a
    • Zynq™-7000, Kintex™-7, Virtex™-7, Artix™-7, Virtex™-6 and Spartan®-6 FPGA Integrated Blocks for PCI Express
    • Kintex™-7 / Virtex™-7 / Artix™-7 x1, x2, x4, x8 Gen 1 and x1, x2, x4 Gen 2
    • Virtex™-6 x1, x2, x4 Gen 1 and x1, x2 Gen 2
    • Spartan®-6 x1 Gen 1
  • Endpoint for Gen1 PCI Express
    • Protocol and electrically compatible
    • Complete endpoint solution includes physical, link and transaction, and configuration management modules
    • Both 8-lane and 4-lane configurations auto negotiate down to a 1-lane configuration
    • Supports packet-oriented LocalLink Interface
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Semiconductor IP