DO-254 AXI Bridge For PCI Express 1.00a

Overview

Key Features

• Zynq™-7000, Kintex™-7, Virtex™-7, Artix™-7, Virtex™-6 and Spartan®-6 FPGA Integrated Blocks for PCI Express
• Kintex™-7 / Virtex™-7 / Artix™-7 x1, x2, x4, x8 Gen 1 and x1, x2, x4 Gen 2
• Virtex™-6 x1, x2, x4 Gen 1 and x1, x2 Gen 2
• Spartan®-6 x1 Gen 1
• Maximum Payload Size (MPS) up to 256 Bytes
• Multiple Vector Messaged Signaled Interrupt (MSI)
• Legacy interrupt supported
• Memory-mapped AXI4 access to PCIe® space
• PCIe® access to memory mapped AXI4 space
• Tracks and manages Transaction Layer Packets (TLP) completion processing
• Detects and indicates error conditions with interrupts
• Optimal AXI4 pipeline support for enhanced performance
• Compliant to Advanced RISC Machine (ARM®) Advanced Microcontroller Bus Architecture 4(AMBA®) AXI4 spec
• Supports up to three PCIe® 32-bit or 64-bit PCIe Base Address Register (BAR) as Endpoint

Benefits

• Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.

Deliverables

• Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.

Technical Specifications