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PCI Express 5.0 IP

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Compare 283 IP from 17 vendors (1 - 10)
  • PCI Express Gen5 SERDES PHY on Samsung 8LPP
    • Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.38 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • Multi-Port Switch IP for PCI Express
    • Designed according to the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
    • Designed according to the PCI-SIG Single-Root I/O Virtualization specification
    • Supports PIPE PHY interface definition including variable clock and variable data
    • Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
    Block Diagram -- Multi-Port Switch IP for PCI Express
  • IDE Security IP Modules for PCI Express 7.0
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
    • FLIT mode support
    • Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
    Block Diagram -- IDE Security IP Modules for PCI Express 7.0
  • PCI Express Gen 1/2/3/4 Phy
    • TSMC advanced 16 nm FFC CMOS process
    • Available in 1X, 4X, 8X, and 16X configuration
    Block Diagram -- PCI Express Gen 1/2/3/4 Phy
  • PCI Express Gen 1/2/3/4 Phy
    • 2.5/5.0/8/16 Gbps per lane interface optimized for PCI Express applications
    • Compliance to PCI Express 1.0a, 1.1 and 2.1, 3.1 and 4.0 PIPE specifications
    Block Diagram -- PCI Express Gen 1/2/3/4 Phy
  • UltraScale+ Device Integrated Block for PCI Express (PCIe)
    • Designed to PCI Express Base Specification 3.1
    • PCI Express Endpoint, Legacy Endpoint or Root Port Port Modes
    • x1, x2, x4, x8 or x16 link widths
    • Gen1, Gen2 and Gen3 link speeds
  • PCI Express Gen 1/Gen 2 Phy
    • 2.5/5.0 Gbps per lane interface optimized for PCI Express applications
    • Conforms to PCI Express Specification 1.0a, 1.1 and 2.0
    • PIPE compliant parallel interface
    Block Diagram -- PCI Express Gen 1/Gen 2 Phy
  • PCI Express 4.0 PHY
    • Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications
    • Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications
    • Supports L1 PM/CPM substates with CLKREQ#
    • Supports the separate REFCLK Independent SSC (SRIS) architecture
    Block Diagram -- PCI Express 4.0 PHY
  • ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
  • PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
    • Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Production-proven datapath support for 32b, 64b, 128b, 256b and 512b implementations
    • Fully compliant with the PCI-SIG Single-Root I/O Virtualization (SRIOV) specification
    • Application interfaces include the Synopsys native interface or the optional ARM® AMBA® 4 AXI and 3 AXI application interface (AMBA not available for Switch configurations)
    Block Diagram -- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
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