PCI Express 4.0 IP
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575
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PCI Express 4.0 PHY
- Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications
- Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications
- Supports L1 PM/CPM substates with CLKREQ#
- Supports the separate REFCLK Independent SSC (SRIS) architecture
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PCI Express - Configurable PCI Express 4.0 IP
- Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
- Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
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PCI Express Gen4 SERDES PHY on Samsung 7LPP
- Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.32 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
- Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.266 mm2 active silicon area per lane including ESD
- Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
- Minimal latency – 3 UI between parallel transfer and serial transmission
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Multi-Port Switch IP for PCI Express
- Designed according to the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
- Designed according to the PCI-SIG Single-Root I/O Virtualization specification
- Supports PIPE PHY interface definition including variable clock and variable data
- Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
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IDE Security IP Modules for PCI Express 7.0
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
- FLIT mode support
- Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
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PCI Express Gen 4 PHY
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
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PCI Express Gen 1/2/3/4 Phy
- TSMC advanced 16 nm FFC CMOS process
- Available in 1X, 4X, 8X, and 16X configuration
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PCI Express Gen 1/2/3/4 Phy
- 2.5/5.0/8/16 Gbps per lane interface optimized for PCI Express applications
- Compliance to PCI Express 1.0a, 1.1 and 2.1, 3.1 and 4.0 PIPE specifications
