Memory Compiler IP
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Memory Compiler
- High-Density Memory Compilers
- Ultra-High-Speed Memory Compilers
- Low-Power Memory Compilers
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Ultra High-Speed Cache Memory Compiler - 2-Port Register File - TSMC N3P
- The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture.
- This architecture enhances system performance, scalability, power efficiency, data locality, application responsiveness, cost optimization, and market competitiveness, providing a distinctive business value.
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Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
- Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
- Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
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Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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TSMC CLN7FF Ternary Content Addressable Memory Compiler with Column Redundancy
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.675V to 0.825V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 32bits to 80K bits.
- Pins and metal layers
- 1P4M (1X_h_1Xa_v_1Ya_h): 4 metal layers used and top metal is MYa
- Power mesh supported with M4 pins
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TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.675V to 0.825V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 32bits to 80K bits.
- Pins and metal layers
- 1P4M (1X_h_1Xa_v_1Ya_h): 4 metal layers used and top metal is MYa
- Power mesh supported with M4 pins
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k
- Foundry Sponsored Memory Instance
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
- To offer several performance trade-offs for any memory size
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TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.675V to 0.825V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 32bits to 80K bits.
- Pins and metal layers
- 1P4M (1X_h_1Xb_v_1Xe_h): 4 metal layers used and top metal is MXe
- Power mesh supported with M4 pins
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TSMC CLN12FFC Ternary Content Addressable Memory Compiler
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.72V to 0.88V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 128bits to 80K bits.
- Pins and metal layers
- General features
- BIST compiler features