Memory Compiler IP
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642
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Ultra High-Speed Cache Memory Compiler
- Up to 3.4 GHz operation in N3P process
- Cache size up to 16 Kb
- 4 – 64-bit word width
- Configurable way associativity
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TSMC CLN7FF Pre-search and Pipeline Ternary Content Addressable Memory Compiler
- Ternary Content Addressable Memory (TCAM) operates within a voltage range from 0.675V to 0.825V and a junction temperature range from -40°C to 125°C. The available supported macro size is configured from 64bits to 80K bits.
- ? Pins and metal layers
- – 1P5M (1X_h_1Xa_v_1Ya_h_1Y_v): 5 metal layers used and top metal is MY
- – Power mesh supported with M5 pins
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TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.675V to 0.825V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 32bits to 80K bits.
- Pins and metal layers
- 1P4M (1X_h_1Xb_v_1Xe_h): 4 metal layers used and top metal is MXe
- Power mesh supported with M4 pins
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TSMC CLN12FFC Ternary Content Addressable Memory Compiler
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.72V to 0.88V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 128bits to 80K bits.
- Pins and metal layers
- General features
- BIST compiler features
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Configuration
- SVT transistors for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- High speed
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Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Source biasing implementation for low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
- Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speed)
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1. Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2. Extend the battery life
- Leakage reduction thanks to careful design structures,optional retention mode and choice of SVT/HVT periphery
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Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
- Decrease of fabrication costs
- Up to 50% denser than traditional register file compilers!
- Ultra low dynamic power
- Low power architecture even at nominal voltage: Up to 50% less consuming than standard memory compilers available at 90 nm LP