MMC IP

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Compare 40 IP from 12 vendors (1 - 10)
  • SD / SDIO / MMC Host Controller
    • Compliant with SD Host Controller Standard Specification Version 2.0
    • Compliant with SD Physical Layer Specification Version 2.0
    • Compliant with SDIO Specification 2.0
    • Compliant with eMMC Specification Version 4.41
    Block Diagram -- SD / SDIO / MMC Host Controller
  • GMSC 0.18um MMC including PRG03,VDT01,POR03,ROSC01
    • Process: GSMC 0.18um 1P4M Generic CMOS process
    • IO style: VeriSilicon v2.1 stagger IO
    • Detail information: in related documentations about GSMC18_PRG_03, GSMC18_ROSC_01, GSMC18_VDT_01 and GSMC18_POR_03
  • SMIC 0.18um Low Leakage MMC Card
    • Process: SMIC 0.18 low leakage 1P4M CMOS process
    • IO style: VeriSilicon v2.1 stagger IO
    • Detail information: refer to the related documents about SMIC18LL_PRG_03, SMIC18LL_ROSC_01 and SMIC18LL_VDT_01
  • SMIC 0.18um Low Leakage MMC Card
    • Process: SMIC 0.18 low leakage 1P4M CMOS process
    • IO style: VeriSilicon v2.1 stagger IO
    • Detail information: refer to the related documents about SMIC18LL_PRG_03, SMIC18LL_ROSC_01 and SMIC18LL_VDT_01
  • SMIC 0.18um Low Leakage MMC Card
    • Process: SMIC 0.18 low leakage 1P4M CMOS process
    • IO style: VeriSilicon v2.1 stagger IO
    • Detail information: refer to the related specifications about SMIC18LL_PRG_03, SMIC18LL_ROSC_01, SMIC18LL_VDT_01B and SMIC18LL_POR_03
  • MMC Target Controller
    • Compliant with MultiMediaCard Spec ver4.X/3.X
    • Supports MMC 1bit, 4bit, 8bit modes, as well as SPI mode
    • Maximum data rate up to 416Mbits/sec
    • All command and response types are supported
  • SMIC 0.13um MMC
    • Process: SMIC 0.13μm 1.2v/3.3v 1P8M Logic process
    • Operating Junction Temperature: -40°C~+25°C~+125°C
    • IO Style: Inline
    • Input Voltage: 1.62v~3.6v
  • Mixed-Mode Clock Manager (MMCM) Module
    • Wrapper around the MMCM_ADV primitive
    • Configurable BUFG insertion
    • Supports all MMCM_BASE and some MMCM_ADV features, as applicable to embedded system designs
  • SMIC 0.18um MMC_07E
    • Process: SMIC 0.18um 1P5M Generic CMOS process
    • More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
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Semiconductor IP