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Search (121)
Compare 121 IP from 22 vendors (1 - 10)
  • LDPC Encoder/Decoder IP Core
    • IPM-LDPC for NandFlash Storage: Adaptable BER, Up to 6 checks per bit, customizable data path
    • IPM-LDPC for short code: option to be full asynchronous, option to be in 3 clock cycles
    • fully configurable: matrix generator, data path, number of iteration checks, packet size
    Block Diagram -- LDPC Encoder/Decoder IP Core
  • LDPC (1723,2048) IIP
    • Compliant with IEEE Standard 802.3.2018 Ethernet specification.
    • Supports full LDPC functionality.
    • Supports the Lower density parity check (1723,2048).
    • Supports the parity generation of 325 bits.
    Block Diagram -- LDPC (1723,2048) IIP
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
  • DVB-S2X Wideband LDPC BCH Decoder
    • Improved performance
    • Improved efficiency w.r.t. Shannon’s limit
    • Finer gradation of code rate and SNR
  • (2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
    • Strong error correction performance
    • Optimized method significantly lower the error floor at minimal cost
    • High throughput with low complexity hardware
    • Early termination technique
  • 5G-NR LDPC Encoder
    • High-throughput design.
    • Low-power and low-complexity design.
    • Block-to-block on-the-fly configuration.
    • AXI4-Stream handshaking interfaces for seamless integration.
  • DVB-C2 LDPC/ BCH Decoder
    • Irregular Parity Check Matrix
    • Layered Decoding
    • Minimum Sum Algorithm
  • SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • ITU 25G PON LDPC Encoder and Decoder
    • Support for code rates 38/45 and 57/67
    • Uncoded block size of 14592 bits
    • Compliant with "Higher speed passive optical networks - Common transmission convergence layer specification, Recommended Standard, ITU-T G.9804.2, October 2021
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Semiconductor IP