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5G LDPC Intel® FPGA IP

Overview

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels. The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

The 5G LDPC-V IP is a complete channel coding IP, optimized for virtual radio access networks (vRAN) and includes the 5G LDCP IP core.

Key Features

  • IP Functionality
    • Encode and decode supported
    • CRC checker module (CRC24B without concatenation)
    • Rate matcher
    • Per-block modifiable code block length and code rate
    • 5G LDPC-V Lite option for reduced resource usage
    • Improved block-error rate (BLER) performance for high reliability signal-to-noise ratios (SNRs) for ultra-reliable low-latency communications (URLLC)
    • Derate matcher
    • By passable hybrid automatic repeat request (HARQ) block
    • Code block segmentation CRC module (CRC24B without concatenation)
    • Per-block modifiable code block length, code rate, and maximum number of iterations
    • Configurable input precision
    • Layered decoder scheduling architecture to double the speed of convergence compared to non-layered architecture
    • Early termination based on the syndrome check using four layers or full syndrome after each iteration
  • Performance Specifications
    • Complies with the 3GPP 5G LDPC specification
    • No external memory requirement
  • User and System Interfaces
    • Avalon®-Streaming (Avalon-ST) input and output interfaces
  • Debug and Test Capabilities
    • Provides C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
    • Testbench and example design available

Block Diagram

5G LDPC Intel® FPGA IP Block Diagram

Technical Specifications

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