LDPC Encoder/Decoder IP Core

Overview

Nand Flash write cycles are limited. An ECC detects and corrects failed operations, increasing the lifetime of the Nand Flash memory. For Nand Flash-based data storage, using an ECC is mandatory to ensure data validity. The IPM-LDPC is based on the LDPC algorithm. The  IPM-LDPC Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs.

In fact IPM-LDPC Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint.

Key Features

  • IPM-LDPC for NandFlash Storage
    • Adaptable BER
    • Up to 6 checks per bit
    • customizable data path
  • IPM-LDPC for short code
    • option to be full asynchronous
    • option to be in 3 clock cycles
  • fully configurable
    • matrix generator
    • data path
    • number of iteration checks
    • packet size

Benefits

  • Full hardware
  • High performance / low latency
  • Low gate count

Block Diagram

LDPC Encoder/Decoder IP Core Block Diagram

Deliverables

  • Verilog RTL source code
  • Simulation environment
  • Technical documentation
  • Technical support

Technical Specifications

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Semiconductor IP