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IEEE 802.3bj Reed-Solomon IP

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  • IEEE 802.3bj Reed-Solomon Forward Error Correction
    • Low latency
    • Supports 100 Gigabits
    • Configuration and status bus
    • Selectable AXI4-Lite interface for status output
  • IEEE 802.3bj Reed-Solomon Encoder and Decoder
    • Compliant with IEEE 802.3bj, Clause 91
    • Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
    • Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols
    Block Diagram -- IEEE 802.3bj Reed-Solomon Encoder and Decoder
  • 100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
    • FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard).
    • 100G Ethernet MAC-friendly interface
  • UltraScale+ Integrated 100G Ethernet Subsystem
    • Optional built-in 100G RS-FEC
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • Requires license key available at no charge
    • 1588 1-step and 2-step hardware time stamping  
  • Ethernet PCS 100G
    • The Ethernet PCS 100G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification.
    • The Ethernet PCS 100G IP supports 100G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 10G/25G.
    Block Diagram -- Ethernet PCS 100G
  • Clause 91 Reed Solomon FEC
    • BASE-TX Core Features
    • BASE-RX Core Features
    • 25G-TX Core Features
    • 25G-RX Core Features
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