Clause 91 Reed Solomon FEC

Overview

The Reed-Solomon Forward Error Correction (RS-FEC) IP Solution implements the RS-FEC sublayer specified in IEEE 802.3by/D3.1. This high through-put design is targeted for demanding, high frequency applications and provides bypass capabilities for direct access to sub designs. The target frequency is 390.625MHz for up to 100Gbps operation.

Key Features

  • BASE-TX Core Features
    • Implements base modules for the RS-FEC transmitter which includes RS encoder, 64b/66b to 256b/257b transcoder and gearbox logic
    • Implements 4x66-bit interface for 64b/66b to 256b/257b transcoder
    • Implements 257-bit to 330-bit gearbox logic for interconnection between transcoder and encoder
    • Implements 330-bit encoder interface for Reed- Solomon code RS(528,514,10) with polynomial specified in 802.3by specifications
    • High through-put, low latency encoder processes 33 symbols in parallel
    • Valid based implementation allows discontinuous data flow and/or bandwidth controlled operation
    • Implements a fixed latency memory-less design with direct access to RS encoder and transcoder blocks
  • BASE-RX Core Features
    • Implements base modules for the RS-FEC receiver which includes RS decoder a, 256b/257b to 64b/66b transcoder and gearbox logic
    • Implements 330-bit decoder interface for Reed- Solomon code (528,514,10) with polynomial specified in 802.3by specifications
    • Implements 330-bit to 257-bit gearbox logic for interconnection between decoder and transcoder
    • Implements 257-bit interface for 64b/66b to 256b/257b transcoder
    • High through-put decoder processes 33 symbols in parallel
    • Decoder provides detection of uncorrectable codewords and corresponding 257-bit blocks are corrupted at transcoder output as per 802.3by specifications
    • Direct access to RS decoder and transcoder blocks is available
  • 25G-TX Core Features
    • Implements all the features of BASE-TX Core
    • Supports 25G codeword marker insertion with markers specified by 802.3by specifications
  • 25G-RX Core Features
    • Implements all the features of BASE-RX Core
    • Implements 330-bit block synchronization state machine as specified in 802.3by specifications.
    • Implements codeword monitor state machine as specified in 802.3by specifications
  • 100G-TX Core Features
    • Implements all the features of BASE-TX Core
    • Supports 100G codeword marker insertion and mapping with markers specified by 802.3bj specifications
    • Implements symbol distribution to four lanes as specified in 802.3bj specifications
  • 100G-RX Core Features
    • Implements all the features of BASE-RX Core
    • Implements 330-bit block synchronization state machine as specified in 802.3bj specifications
    • Implements alignment state machine as specified in 802.3bj specifications

Technical Specifications

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Semiconductor IP