I3c device IP

The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C bus is used for various sensors in the mobile/automotive system where an I3C Host Controller transfers data and control information between itself and various sensor devices.

The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C bus is used for various sensors in the mobile/automotive system where an I3C Host Controller transfers data and control information between itself and various sensor devices.
The I3C Device Controller IP can be easily integrated into the Sensor/Device Controllers with minimal gate count.

The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices.
The I3C Host Controller implements support for legacy I2C Device Controllers, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support.

The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stack.
The MIPI I3CⓇ Total IP solution is a simplified, backward compatible with I2C, scalable, and cost-effective interface.

The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices.
The I3C Host Controller IP Core provides a 32-bit AHB bus as the application interface to configure and control the I3C Host Controller IP Core.

The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the widely - used I2C protocol.
It was developed by the MIPI Alliance, a global organization that aims to develop interface specifications for mobile devices.

I3C SDR Mode
SDR private read/write data transfers
I3C HDR-DDR Mode
HDR-DDR enter and exit patterns, command coding, bus turnaround, DDR Flow Control Elements and error detection

The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no local host processor.
The DB-I3C-S-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
The DB-I3C-S-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec ver1_0 specification.

The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock.
The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.

I3C Device IP