The MIPI I3C Controller IP is a highly optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and FPGA technologies. The Chip Interfaces MIPI I3C IP is used to connect multiple Targets to one or more Controllers with Secondary controllers having the capability to take ownership of the bus. The IP can act as the Bus Controller or Secondary Controller with the inclusion of the Target Engine, it is also possible to set up as a simple Target or Composite Device with multiple Virtual Targets. The MIPI I3C IP from Chip Interfaces supports SDR and HDR transmission modes over a single or multiple lanes allowing it to reach transfer speeds of up to 100 Mbps. The Chip Interfaces MIPI I3C Controller IP is backward compatible with MIPI I3C versions 1.1 and 1.0, as well as with I2C. The Application data interface follows the TCRI v1.0 specification.
The Chip Interfaces MIPI I3C Controller IP core has been heavily tested in System Verilog random regression environment.
The MIPI I3C Controller IP core is a highly optimized Silicon Agnostic implementation of the MIPI I3C protocol version 1.1.1 and MIPI TCRI v1.0. It is used to connect I3C and I2C target devices over a shared 2-wire bus, targeting both ASIC and FPGAs. It delivers all features of the standard and allows for the ability to configure included features.
Composite Device
The MIPI I3C Design allows for the creation of a composite device, connecting multiple I3C targets over a single physical I3C bus connection. Such an approach reduces the bus capacitance, and other electrical limitations compared to a solution of multiple individual targets connected to the bus.
Even though all targets use the same I3C connection, the host can address and retrieve data from each target independently as needed. This approach saves AISC resources such as area and power consumed.
