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HBM2 IP

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Compare 27 IP from 9 vendors (1 - 10)
  • HBM2 PHY for Samsung
    • Lowest latency for data-intensive applications
    • Advanced clocking architecture minimizes clock jitter
    • Highest data rates with high-resolution delay adjust
    • Designed for optimized interposer routing
  • HBM2 Controller IP
    • Supports HBM2 protocol standard JESD235 and JESD235A Specification
    • Compliant with DFI version 4.0 or 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • HBM2 Memory Controller
    • Support Pseudo Channel mode with 64DQ per Pseudo Channel
    • Support DFI1:1
    • Support HBM Burst Length 4
    • Support 4 High or 8 High HBM Devices
  • HBM2/2E Memory Controller Core
    • Supports HBM Gen2 pseudochannel and Gen1 legacy modes
    • Supports up to 1.2 GHz HBM operation (2.4 Gbps/pin)
    • Dual and single controller options available
  • DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
    • Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
    • uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
    • LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
  • DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
    • Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
    • uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
    • LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
  • HBM2E PHY V2 in TSMC (N7, N6, N5)
    • Low latency, small area, low power
    • Compatible with JEDEC standard HBM2/HBM2E SDRAMs
    • Data rates up to 2400 Mbps for HBM2 and 3600 Mbps for HBM2E
    • 4H and 8H HBM2/HBM2E SDRAM stacks supported
  • HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5)
    • Low latency, small area, low power
    • Compatible with JEDEC standard HBM2/HBM2E SDRAMs
    • Data rates up to 2400 Mbps for HBM2 and 3600 Mbps for HBM2E
    • 4H and 8H HBM2/HBM2E SDRAM stacks supported
  • TSMC CLN7FF HBM2E PHY IP
    • High Bandwidth Memory (HBM2E) DRAM PHY
    • Supports HBM 3.2Gbps
    • Supports DFI 1:2
    • Supports only BL4
  • TSMC CLN5FF HBM PHY IP
    • High Bandwidth Memory (HBM) DRAM PHY
    • Supports HBM 3.6Gbps
    • Supports DFI 1:2
    • Supports only BL4
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