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Search (262)
Compare 262 IP from 52 vendors (1 - 10)
  • Reed Solomon Decoder and Encoder FEC
    • High performance Reed Solomon IP Core (Encoder and Decoder)
    • Supports error and erasure decoding
    • Parameterized codeword length
  • Generic Polar FEC Encoder and Decoder
    • Fully-pipelined architecture
    • Support for systematic and non-systematic encoding
    • Support for coded block lengths of up to 1024 bits
    • Support for a wide variety of
  • oFEC Encoder and Decoder
    • OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
    • The oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach.
    Block Diagram -- oFEC Encoder and Decoder
  • 25G/10G/SGMII/ 1000BASE-X PCS and MAC
    • OmegaCORE 25G/10G/SGMII/1000BASE-X PCS and MAC is the fully integrated Physical Coding Sublayer (PCS), KR FEC (IEEE Clause 74 – fire code FEC), SGMII/1000BASE-X and Media Access Controller (MAC) core for 25Gbps, 10Gbps, 2.5Gbps/1.25Gbps Ethernet applications which is complaint with IEEE 802.3 standard and SGMII specification 1.6.
    • The interface to the PMA supports a single channel Quad mode bidirectional, serial interface. The PCS sublayer supports both 64/66B encoding (10GE) and 8B10B encoding (SGMII/1000BASE-X) with an optional FEC layer function for backplane (10G-KR) application.
    Block Diagram -- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
  • Multi-channel DVB-C / J83 FEC encoder
    • The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 Annexes A B and C.
    • It is designed to interface to external modulators or advanced upconverting DACs such as the Analog Devices AD9789.
    Block Diagram -- Multi-channel DVB-C / J83 FEC encoder
  • DVB-Satellite FEC Decoder
    • The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
    • The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.
    Block Diagram -- DVB-Satellite FEC Decoder
  • Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
    • Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targeted to network infrastructure and data centers.
    • The Low Latency 100G Ethernet Intel® FPGA IP core is compliant with the IEEE 802.3ba-2010 standard, it includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.
    • It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Intel® Stratix® and Intel® Arria® FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules

     

    Block Diagram -- Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
  • Reed Solomon FEC Codec
    • Reed Solomon IP core codec is based on IEEE 802.3bj Clause 91 specification.
    • The cyclic code used is RS (528,514) for 7 symbol error correction and RS (544,514) for 15 symbol error correction.
    • Encoder and Decoder are separate synthesizable cores. Different architectures are available to meet area and throughput requirements. 
  • JESD204 CYCLIC FEC IIP
    • Compliant with JESD204 specification JESD204C.
    • Supports Full JESD204C FEC functionality.
    • This FEC(Forward Error correction) methodology implements the (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661).
    • Supports FEC of 26 bits parity bits.
    Block Diagram -- JESD204 CYCLIC FEC IIP
  • FEC RS (544,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (544,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (544,514) IIP
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