DVB IP

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Compare 138 IP from 23 vendors (1 - 10)
  • DVB-C Demodulator
    • DVB-C EN 300 429 & ITU-T J.83 Annex A & Annex C compliant QAM demodulator
    • Supports IF input
  • Synthesized RTL of DVB CI controller IP-core
    • DVB Common Interface Host
    • Full support of EN 50221 and TS 101 699
    • Flexible timings
    • APB 3.0 interface for programming
  • DVB-S2 Demodulator
    • Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2)
    • Supports CCM mode for broadcasting. ACM and VCM modes will be available soon
    • Support for QPSK and 8-PSK modulations. 16-APSK and 32-APSK will be available soon
    • Support for short blocks (16200 bits) and long blocks (64800 bits)
  • DVB-RCS2 Turbo Decoder
    • Compliant with ETSI 301 545-2 V1.1.1 (2012-01) (DVB-RCS2)
    • Support for all DVB-RCS2 payload
      block sizes (14 to 599 bytes) and code rates (1/3 to 7/8)
    • Support for all modulation schemes
      (QPSK, 8-PSK, 16-QAM)
  • DVB-S2 BCH and LDPC Encoder and Decoder
    • Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
    • Support for short blocks (16200 bits) and long blocks (64800 bits).
    • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
    • Support for all interleaving schemes of all modulation schemes.
  • DVB Remultiplexer N-to-M
    • Drop-in module for Spartan 6, Virtex-6, Artix-7, Kintex-7, Zynq FPGAs
    • N SPI input / M SPI output (N and M from 1 to 8)
    • Adapt one or several MPTS/SPTS stream into one or several MPTS by filtering and multiplexing complete services
    • SFN MIP table insertion independent for each output (for DVB-T core control)
    Block Diagram -- DVB Remultiplexer N-to-M
  • DVB-S2X Wideband LDPC BCH Decoder
    • Improved performance
    • Improved efficiency w.r.t. Shannon’s limit
    • Finer gradation of code rate and SNR
  • DVB-C2 LDPC/ BCH Decoder
    • Irregular Parity Check Matrix
    • Layered Decoding
    • Minimum Sum Algorithm
  • DVB-T2 Demodulator and LDPC/ BCH Decoder
    • DVB-T2 EN302 755 V1.2.1, Rev.9 compliant
    • Supports IF input
    • Single input – Single output (SISO)
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Semiconductor IP