The DVB-S2 LDPC-BCH block is a powerful FEC
(Forward Error Correction) subsystem for Digital
Video Broadcasting via Satellite.
DVB-S2 LDPC BCH Decoder and Encoder
Overview
Key Features
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
- BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
- ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
- Long and short frame lengths
- No error floor to QEF in Standard
- Easy to integrate within receiver
- All code rates and modulation orders
Benefits
- Improved performance
- Improved efficiency w.r.t. Shannon’s limit
- Very high data rate
Applications
- DVB-S2
Deliverables
- Synthesizable Verilog
- System Model (Matlab)
- Verilog Test Benches
- Documentation
Technical Specifications
Maturity
silicon proven
Availability
immediately
Related IPs
- DVB-S2 BCH and LDPC Encoder and Decoder
- DVB-S2X Wideband BCH and LDPC Decoder
- 1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
- DVB-C2 Receiver (including LDPC and BCH decoder)
- IEEE 802.11n/ac/ax (WiFi) LDPC Decoder and Encoder
- LDPC Decoder and Encoder that supports DVB-S2 DVB-S2X DVB-T2 DVB-C2 CMMB DMB-T