Centar IP
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LTE Single Carrier FFT Circuit
- High Throughput: obtained from high clock rates (>400MHz using 65nm technology) and novel algorithms
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Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
- FFT size: Any size power-of-two or non-power-of-two
- Dynamic Range: IEEE754 single precision floating point
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Non-Power-of-Two FFT
- Sample Rates: Very high clock speeds
- FFT size: any size set of transforms (chosen at run-time) factorable into bases up to ~10
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Fixed-size streaming FFT
- High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
- FFT size: Any size power-of-two or non-power-of-two
- Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization (~6db/bit).
- Scalability: array based architecture means higher throughputs are obtained by increasing array size
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Variable FFT (run time choice of FFT size)
- High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
- FFT size: any user chosen set of power-of-two or non-power-of-two sizes chosen at run-time (e.g., 128/256/512/1024/2048 points for LTE/WiMax OFDMA)
- Programmability: Simple control circuitry for matching circuit/application functionality and I/O interface.
- Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post-processing operations such as equalization.
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Single precision fixed-size streaming floating-point FFT
- FFT size: Any size power-of-two or non-power-of-two
- Dynamic Range: IEEE754 single precision floating point