Baseband IP

The Ceva-BX2 baseband processor IP handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming.
It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size.
Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators.

Supports data rates upto 65Mbps
Throughput numbers of above 50 Mbps for UDP and above 40 Mbps for TCP.
Support for authentication methods (Cisco® LEAP, PEAP with EAP-GTC support, CCKM with EAP-FAST) depend on the host platform.
Supports MAC enhancements including:802.11d -Regulatory domain operation,802.11e -QoSincluding WMM,802.11h –Transmit power control dynamic and frequency selection,802.11i -Security including WPA2 and WAPI compliance,802.11k -Radio resource measurement,802.11r –Roaming,802.11w -Management frame protection

PLC G3 physical layer (PHY) compliant baseband processor as per ITU-T G.9903 Chapter 7 and ITU-T G.9901 Annex B.

Small signal digital clock buffer for baseband application;
Cell Size (Width * height)90um * 180um with DUP stagger bonding pads;
Work voltage: 1.2V power;
Support >600mV clock signal input;Support 0.3V~0.5V wide input offset voltage range;

Supports ECMA-368 PHY requirements for mandatory rates (53.3, 106.7 and 200 Mbps)
Advanced acquisition and channel estimation algorithms to support SNR of < -3 dB
Streaming mode support
Low power implementation techniques with advanced clock management logic