BPSK IP

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Compare 58 IP from 25 vendors (1 - 10)
  • Burst-mode BPSK Modem with highly efficient packet structure
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • Binary-PSK Demodulator
    • 16-bit signed input data samples
    • Automatic carrier acquisition
    • Fast carrier acquisition time
    • No complex PLL setup or tuning required
    Block Diagram -- Binary-PSK Demodulator
  • MIMO Decoder
    • Includes QR Decomposition, Dynamic scale and  K-best Decoder
    • Fixed Depth K-Best Decoder (K=16)
    • Achieves close-to ML BER performance
    • Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
    • Supports square and non-square QAM
    Block Diagram -- MIMO Decoder
  • K-Best MIMO 3×3 Decoder
    • Fixed Depth K-Best Decoder (K=16)
    • Achieves close-to ML BER performance
    • Supports three streams with different QAM (from BPSK to 64 QAM)
    • Supports square and non-square QAM
    • Supports OFDM based systems with different Space Time Coding (STC)
    Block Diagram -- K-Best MIMO 3×3 Decoder
  • OFDM - Orthogonal Frequency Division Multiplexing
    •  Configure and create complete multiple OFDM Frames with Preamble, Header, and Payload
    •  Preset for Standard compliant Frames for various wireless standards like Wi-Fi, WiMAX
    •  Define Frame with Preamble, Header, and Payload (selectively) to simulate different OFDM signals
    Block Diagram -- OFDM - Orthogonal Frequency Division Multiplexing
  • Ultra-low-power 60 GHz radar-on-chip
    • CSEM has developed a low-cost, ultra-low-power 60 GHz MIMO FMCW PHY that can be integrated into radar-on-chips with custom digital processing for specific applications.
    • This solution leverages CSEM’s decades of experience in ultra-low-power RF CMOS system-on-chip design.
    Block Diagram -- Ultra-low-power 60 GHz radar-on-chip
  • 802.11ah IP - GLOBALFOUNDRIES 22nm FDX
    • Process Technology: GLOBALFOUNDRIES 22nmFDX
    • Operation voltage: core 0.8v, I/O 1.8v
    • Operation Band:  863MHz ~ 928MHz
    • Power and clock blocks are integrated in IP
    Block Diagram -- 802.11ah IP - GLOBALFOUNDRIES 22nm FDX
  • LDPC for 5G DVBS2 802.11
    • High throughput
    • One encoder and decoder per matrix
    • Five cycles per iteration may increase to around 10 for timing between gates.
    • Has configuration parameters for stopping if code is diverging.
  • DVB-T2 Demodulator and LDPC/ BCH Decoder
    • DVB-T2 EN302 755 V1.2.1, Rev.9 compliant
    • Supports IF input
    • Single input – Single output (SISO)
  • DVB-RCS2 Multi-Carrier Receiver
    • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
    • Support for Linear Modulation Bursts of Table A-1
    • Optional support for Spread-spectrum Linear Modulation Burst waveforms of Table A-2
    • Support for BPSK, QPSK, 8-PSK, 16-QAM
    Block Diagram -- DVB-RCS2 Multi-Carrier Receiver
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