Andes IP
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48
IP
from 4 vendors
(1
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10)
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Superscalar Out-of-Order Execution Multicore Cluster
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
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Compact, Secure and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Andes extensions for performance and code size enhancements
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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RISC-V CPU IP With ISO 26262 Full Compliance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions
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64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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64-bit CPU Core with Level-2 Cache Controller
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
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Compact High-Speed 32-bit CPU Core with Level-2 Cache
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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Compact High-Speed 32-bit CPU Core with MemBoost and PMA
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
