Andes IP
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ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D
- D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
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8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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Superscalar Out-of-Order Execution Multicore Cluster
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
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Compact and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant with RISC-V I, M, A, C, B and Zce extensions
- Andes extensions for performance and code size enhancements
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Compact, Secure and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Andes extensions for performance and code size enhancements
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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RISC-V CPU IP With ISO 26262 Full Compliance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions
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64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
