Register, Configuration and Control Bus

Overview

Key Features

• Data Paths
• Multiplexed address and data bus for minimum interconnect
• 8, 16, 32 … or any width of address and data bus
• Custom bus widths may be specified
• Protocols
• Simple master and target interfaces
• Clock rate independent protocols
• Single protocol for all performance levels
• Multiple master and target capability
• Multi-segment capability
• Direct attach of ARC host and auxiliary buses
• Addressing
• Customizable assignment of address space
• ARC debug compatible
• Devices
• Any number of transaction initiators
• Any number of transaction targets
• Arbitration
• User configurable/customizable
• Base algorithms provided : Round-robin
• Fabric
• Parallel OR-gate multiplexing
• Serial point-to-point
• Pipelined point-to-point
• Bridges (Gateways)
• On-chip between segments
• Interfaces
• Initiator and Target TAPs: Simple synchronous protocol, Clock domain transition support
• Industry standard veneers: A2B, OCP-IP; VSIA (BVCI, PVCI), AMBA on request
• Extensions
• Parity protection
• Error protocol
• User-defined bus fields
• Bus monitoring

Benefits

• Local interconnections between sub-modules are often configured using an OR structure as the A2R fabric and inter-module connections are configured to use a ring structure. This point-to-point topology can then be pipelined so that all sections of the ring settle within a single clock cycle this allows the A2R to be configured such that only single cycle operations exist and no false path or multi-cycle paths exist which significantly eases timing closure in large SoC designs.

Deliverables

• Verilog RTL
• Verilog Testbench
• Specification

Technical Specifications