FPD LVDS Display Interface, 1 Port / 2 Port LCD Panel

Overview

The DB-FPD-LVDS-TX LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 or 5 LVDS Differential Data Pairs and 1 LVDS Differential Clock Pair.

The DB-FPD-LVDS-TX LVDS licenses with the DB9000 Display Controller family IPs, for the licensing options of driving LVDS Interfaces panels.

Key Features

Supports 3 and 4 and 5 data and 1 clock LVDS differential pairs
18 / 24 bits-per-pixel (typically RGB or YCbCr)
Example Range of Video Formats:
- HD 1280x720p
- Full HD 1920x1080p
- Cinema Full HD 2560x1080p
- UHD 4K x 2K 3840x2160p
Single, Dual, Quad Port LVDS Panel Support Provided
Supports standardized FPD-Link Panels, V-by-One HS Drivers
Compatible with commercial LVDS ICs:
- SN65LVDS*, SN75LVDS*,DS90CR*, DS90UR*, THC63LVD
Supports 600-800 Mbps per data pair (Technology Dependent)
Differential Driver per data pair supplied by user from foundry technology library
Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Block Diagram

Deliverables

The DB-FPD-LVDS-TX is available in synthesizable RTL Verilog or a technology specific netlist for FPGAs, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual.

Technical Specifications

Foundry, Node

IBM, LSI. TMSC, UMC, Tower

Maturity

Successful in Company FPGA Kit Demo Reference Design, Customer Products

Availability

Immediately

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