The multi-channel Stream Direct Memory Access (SDMA) controller IP core provides high bandwidth direct memory access between memory and any IP peripherals with an AXI4-Stream interface for up to 16 channels.
The SDMA IP utilities a dedicated Write and Read circular buffer structure for data and descriptor(s) for each DMA channel, which helps in offloading data movement tasks from the Central Processing Unit (CPU) in processor-based systems.
Configuration of status and management registers are accessed through an AXI4-Lite interface. Control and Status streaming interfaces are used for sending/receiving user application data. Interrupts are available to indicate error and completion events.
