Via ROM IP
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CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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CSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- Low Leakage
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
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CSMC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
- Reduce the die cost
- Via 1 programmable ROM
- Key patent for high density with only one programming
- layer
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sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- REDUCE DIE COST
- 35% denser than alternative solutions on the market
- Key patent for high density with a single programming layer
- Via 1 programmable ROM
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Ultra-low-leakage even in a generic process
- No leakage in memory plane
- Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
- Key patent for high density with only one programming layer
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Foundry sponsored memory generator
- For nominal voltage characterization corner
- Configuration
- Dolphin's SVT bit-cell and HVT transistors for periphery
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
- Power reduction features
- Decrease of packaging cost
- Smaller SoC area
- Decrease of fabrication costs
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
- Foundry sponsored memory generator
- For nominal voltage characterization corner
- Power reduction features
- Up to 50% gain in dynamic power consumption compared to standard ROM
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Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k
- For nominal voltage characterization corner
- Power reduction features
- Up to 50% gain in dynamic power consumption compared to standard ROM
- Decrease of fabrication costs