IP Catalog > Memory Controller/PHY IP

Memory Controller/PHY IP

Memory Interface IP cores support a wide range of memory types and standards, including DDR IP (Double Data Rate), GDDR IP (Graphics Double Data Rate), HBM IP (High Bandwidth Memory), and LPDDR IP (Low Power DDR), ensuring optimal performance in applications such as gaming, data centers, and mobile devices. NVM Express IP offers high-speed, low-latency storage interface for solid-state drives, while ONFI IP supports NAND flash memory communication. Additionally, SAS IP (Serial Attached SCSI) and SATA IP (Serial ATA) enable reliable, high-performance storage solutions, and SD/eMMC IP cores facilitate efficient data transfer for embedded systems.

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Search (1,344)
Compare 1,344 Memory Controller/PHY IP from 77 vendors (1 - 10)
  • SATA-III Host Controller
    • Fully compliant with the Serial ATA specification revision 2.6
    • Simple transaction interface with Host processor and DMA Engine
    • 32-bit internal data path
    • 8KB FIFO implemented by BlockRAM in both transmit and receive paths
    Block Diagram -- SATA-III Host Controller
  • SATA-II Host Controller Core
    • Fully compliant with the Serial ATA specification revision 2.6
    • Simple transaction interface with Host processor and DMA Engine
    • 32-bit internal data path
    • 8KB FIFO implemented by BlockRAM in both transmit and receive paths
    Block Diagram -- SATA-II Host Controller Core
  • AMBA AHB Bus to DDR SDRAM Controller
    • External pin reduction by transferring 2 bits of data per pin.
    • Supports multiple external SDRAM banks.
    • Automatic refresh generation with programmable refresh intervals.
    • Self-refresh mode to reduce system power consumption.
    • Standard delay cells or user provided DLL for DQ and DQS alignment.
    Block Diagram -- AMBA AHB Bus to DDR SDRAM Controller
  • AMBA AHB Bus to SDRAM Controller
    • SDRAM controller interfaces directly with AHB Bus and user interface.
    • Built-in arbitration between two access ports.
    • Second access port allows memory sharing with user logic devices.
    • Dual write buffer for simultaneous write posting and SDRAM access.
    Block Diagram -- AMBA AHB Bus to SDRAM Controller
  • Pipeline SDRAM Controller
    • Designed with synthesizable HDL for ASIC and PLD synthesis.
    • Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
    • Supports register mode and non-register mode SDRAM DIMM.
    • Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
    Block Diagram -- Pipeline SDRAM Controller
  • DDR SDRAM Controller
    • Supports industry standard Double Data Rate (DDR) SDRAM.
    • Designed for ASIC and FPGA implementations in various system environments.
    • Programmable memory size and data width.
    • Supports industrial standard 64Mbit, 128Mbit and 256Mbit DDR SDRAMs.
    Block Diagram -- DDR SDRAM Controller
  • DDR2 SDRAM Controller
    • Supports industrial standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
    • Page hit detection to support multiple column accesses within the same row.
    • Pipeline access enables continuous data bursting and hidden active commands, even in the case of page misses.
    • Issue precharge, active and read/write commands to multiple banks at the same time.
    Block Diagram -- DDR2 SDRAM Controller
  • DDR3 SDRAM Controller
    • Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM.
    • Pipeline access allows continuous data bursting and hidden command execution.
    • Page hit detection supports fast column access and multiple open banks.
    • High speed implementation with standard DFI support for hard DDR PHY.
    Block Diagram -- DDR3 SDRAM Controller
  • NAND Flash Controller
    • Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
    • Supports 1, 4 and 8 bit ECC correction per 512byte.
    • Uses Hamming code for SLC and BCH code for multi-bit correction in MLC.
    • Programmable support for large block and small block NAND Flash devices with 512, 2k and 4k byte page sizes.
    Block Diagram -- NAND Flash Controller
  • Flash/ROM/SRAM Controller
    • Supports industry standard Asynchronous SRAM, NOR Flash, ROM and similar memory devices.
    • Two request ports to allow two requesters to share access to the FLASH/ROM/SRAM devices.
    • 8 Chip select signals to access up to 8 memory banks.
    • Independent programmable timing parameters for each chip select.
    Block Diagram -- Flash/ROM/SRAM Controller
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