PCI Express Phy IP

Compare 163 PCI Express Phy IP from 22 vendors (1 - 10)

1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- High speed performance
- Low power architecture
- Robust training
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
- Fully compliant with PCI Express Base 5.0 electrical specifications
- Compliant with PIPE5.2 (PCIe) specification
- Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
High Performance, Low Latency PCIe Gen5 PHY
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features
PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features
PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features
PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features