PCI Express Phy IP
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PCI Express Phy IP
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312
PCI Express Phy IP
from 23 vendors
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10)
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1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- High speed performance
- Low power architecture
- Robust training
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PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
- Fully compliant with PCI Express Base 5.0 electrical specifications
- Compliant with PIPE5.2 (PCIe) specification
- Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
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PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
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PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
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High Performance, Low Latency PCIe Gen5 PHY
- 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
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PCIe 2.0 PHY, UMC 40LP, x1
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
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PCIe 2.0 PHY, UMC 40LP x4, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
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PCIe 2.0 PHY, UMC 40LP x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
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PCIe 2.0 PHY, UMC 28HPC+ x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
