PCIe Gen3 PHY

Overview

Key Features

• Standards Compliance
• PCI Express Base Specification 3.1
• Supported Lane widths of x1, x2, x4, x8, x16
• Data bus widths support encoding as per:
• Gen3: 128b/130b
• Gen1/2: 8b/10b
• IEEE 1149.1
• High-Speed data transfer up to 8Gbps per lane
• Low Power
• Self-tuning architecture: no training patterns or user configuration required
• Fully adaptive continuous-time equalizer with automatic gain control analog front end (AFE) combined with adaptive multi-tap decision feedback equalization (DFE) to cover Channel variations and PVT
• 3-TAP TX FIR with programmable coefficients
• Clocking with various input frequencies
• Clocking options for external reference or internal clock for debug
• DSP based second order timing recovery with spread-spectrum clock tracking
• On-Chip IO ring compatibility
• Designed as an IO-ring component
• Small footprint
• Flip-Chip packaging
• Test and Debug Features
• Loopback serial and parallel
• Scan
• JTAG
• Serial Debug
• Configurability
• Programmable lane enable/disable
• Choice of macros pre-configured for 1 to 16 lanes

Benefits

• Low Risk - Silicon proven with Si characterization data
• Excellent Interoperability
• Superior Noise Immunity - Fully differential circuitry and Voltage Regulator for enhanced noise immunity
• Minimal Area for flip-chip package
• Improve Test Coverage - Multiple loopback modes with 12 built-in patterns
• Scan built in to all digital, Serial Control Register (SCR) for simplified testing, JTAG support (DC & AC )
• Lowest Total Cost of Ownership
• Customization/ Integration support

Block Diagram

Applications

• Consumer
• Server
• Industrial

Deliverables

• Abstract LEF
• Behavioral Model Verilog
• Timing Model .lib
• High-speed IO Model hSpice
• LVS Netlist cdl
• Physical database GDSII
• Documentation pdf

Technical Specifications