Security IP for TSMC
Welcome to the ultimate Security IP for TSMC hub! Explore our vast directory of Security IP for TSMC
All offers in
Security IP
for TSMC
Filter
Compare
43
Security IP
for TSMC
from 9 vendors
(1
-
10)
-
1G to 50G Single-Port MACsec Engine with xMII interface and TSN support
- MACsec solution for integration between MAC and PCS side supporting 1GbE to 50GbE rates with optional TSN support (including IEEE803.2br).
- For MACsec function integrates the MACsec-IP-161 with all IEEE MACsec standards supported. Optional Cisco ClearTags.
- Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
-
800G Multi-Channel MACsec Engine with TDM Interface
- Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
- All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
- Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
-
Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
-
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
- 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
-
NIST ESV certified, AIS-31, FIPS (SP800-90A/B/C) True Random Number Generator
- Non-deterministic Random Number Generator, FIPS-140 SP800-90A/B compliant, ESV certified for NRBGs and DRBGs (#E167).
- High performance, low power, fully digital, standard cell only, supports all CMOS nodes.
- Available as standalone RBG or embedded in the Rambus RT-130, RT-630, RT-660 Root of Trusts
-
Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
- 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
-
Multi-Protocol Engine, Look-Aside, 1 Gbps
- Protocol-aware IPsec/TLS packet engine with Look-Aside interface for IoT.
- Up to 1 Gbps, lowest gate count in the industry, just 100K gates (ex AMBA interface).
- Supported by Driver Development Kit, QuickSec IPsec toolkit, Secure Boot Toolkit.
-
TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
-
TESIC CC EAL5+ Secure Element IP Core
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
-
MACsec 10G/25G
- Compliance with IEEE Std 802.1AE-2018
- Line-rate traffic encryption and decryption
- Supports 10G/25G data rates
- Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
