Security IP for TSMC
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39
Security IP
for TSMC
from 8 vendors
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10)
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800G Multi-Channel MACsec Engine with TDM Interface
- Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
- All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
- Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
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Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
- 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
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NIST ESV certified, AIS-31, FIPS (SP800-90A/B/C) True Random Number Generator
- Non-deterministic Random Number Generator, FIPS-140 SP800-90A/B compliant, ESV certified for NRBGs and DRBGs (#E167).
- High performance, low power, fully digital, standard cell only, supports all CMOS nodes.
- Available as standalone RBG or embedded in the Rambus RT-130, RT-630, RT-660 Root of Trusts
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Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
- Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
- 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
- Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
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Multi-Protocol Engine, Look-Aside, 1 Gbps
- Protocol-aware IPsec/TLS packet engine with Look-Aside interface for IoT.
- Up to 1 Gbps, lowest gate count in the industry, just 100K gates (ex AMBA interface).
- Supported by Driver Development Kit, QuickSec IPsec toolkit, Secure Boot Toolkit.
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MACsec 10G/25G
- Compliance with IEEE Std 802.1AE-2018
- Line-rate traffic encryption and decryption
- Supports 10G/25G data rates
- Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
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NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
- Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
- Supports both encryption and decryption functions.
- Supports 128/192/256-bit Cipher keys.
- Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
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802.11i CCMP/TKIP IP Core
- Small size:
- Includes key lookup, encryption, decryption, header parsing and modification, key expansion and data interface
- Uses external memory for key storage;
- Configurable number of keys supported; 64 bytes are required per bidirectional link
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RC4 Keystream Generator
- Keystream generation using the RC4 algorithm
- Small size: from 20K ASIC gates
- Satisfies the ARC4 specification
- Capability to save and restore internal state using a data bus with parameterized width.
