LVDS IP for TSMC

Compare 6 LVDS IP for TSMC from 2 vendors (1 - 6)

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16nm

2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
- AD_SLVS_LVDS is a highly conﬁgurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is ﬂexible enough for any system.
- To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm.
- This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.
1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
- A TSMC 28nm HPM/HPC/HPC+ Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, 5V I2C ODIO, 1.8V & 3.3V Analog Cells, ESD and more.
- A key attribute of this silicon-proven library is to detect and adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
- The GPIO can be configured as input, output, open-source, or open-drain with an optional 60kohm pull-up or pull-down resistor.
LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
- The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
- The polarity of differential signals for each data lane can be controlled.
IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- Certus offers dedicated 1.8V, 3.3V and switchable 1.8V/3.3V General-Purpose IO (GPIO) solutions.
- GPIO features include:
- I2C / SMBUS Open-Drain I/O features include:
- LVDS I/O features include:
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
- I2C Open-drain
- Physical Features
High-voltage solutions in baseline GlobalFoundries and multi-foundry technologies
- High-Voltage ESD
- Physical Features