IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes

Overview

Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet offerings. Our I/O solutions include 1.8V & 3.3V GPIO, I2C, SMBUS, open-drain, RGMII, SD, LVDS, HDMI and more.
Drawing from this rich database, Certus has a starting point from which we can create any custom additions you may need. Our building-block design style also enables us to configure our IOs to fit a variety of cell sizes, aspect ratios, pad arrangements and packages. We work closely with our clients to provide tailored solutions affordably and with fast turnaround.

Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we address standard ESD such as HBM and CDM, but we can also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).

Key Features

Certus offers dedicated 1.8V, 3.3V and switchable 1.8V/3.3V General-Purpose IO (GPIO) solutions.
GPIO features include:
- Dedicated 1.8V & 3.3V cells or dynamically switchable 1.8V/3.3V cell
- Multiple drive strengths (dedicated cells or selectable)
- Supply sequence independence
- Output enable / disable (HiZ when disabled)
- Schmitt trigger input
- Selectable pull-up or pull-down resistor
- Flexible metal stack and cell pitch variations
- Wirebond & Flip-Chip support
I2C / SMBUS Open-Drain I/O features include:
- Up to 5V external supply support
- Hysteresis input
- Power sequence independence
- External resistor support of 1K-50K Ohm
- Fail-safe protection
- 2KV HBM, 500V CDM
- Also DDC, CEC and HPD compliant
LVDS I/O features include:
- Output enable (TX)
- Input enable (RX)
- Internally generated common mode reference (no external pin required)
- Built-in 100? RX termination resistor
- Fault-safe mode for shorted or open RX pins
- Power-on sequence independence
- ESD protection of 2KV HBM, 500V CDM

Benefits

High confidence level for first time-right IC ESD design backed by SPICE simulation, optimization and verification methodology including HBM & CDM specifications
Highly area-efficient solutions allowing for IO height reductions of typically > 20% compared to standard foundry IOs
Portable & foundry proven
Si product proven IP in most advanced CMOS from 180nm down to 12nm
Uniform ESD protection levels with more effective CDM protection
Standard, full custom libraries plus IO template library offering
Fast turnaround custom IO library designs

Block Diagram

Deliverables

GDS
CDL netlist
Verilog stub
Verilog behavioral model
LEF
Liberty Timing Files
IBIS (option)
Electrical datasheet
User guide and application notes
Consulting and Support

Technical Specifications

Foundry, Node

TSMC 180nm, 130nm, 65nm, 28nm, 22nm, 16nm & 12 nm

Maturity

Silicon-Proven

TSMC

In Production: 12nm , 16nm , 22nm , 28nm HPCP , 28nm HPM , 65nm G , 65nm GP , 65nm LP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD , 180nm G , 180nm LP , 180nm LV

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