Embedded Memories IP for TSMC
Welcome to the ultimate
Embedded Memories IP
for
TSMC
hub! Explore our vast directory of
Embedded Memories IP
for
TSMC
All offers in
Embedded Memories IP
for
TSMC
Filter
Compare
71
Embedded Memories IP
for
TSMC
from
13
vendors
(1
-
10)
-
Embedded flash IP, 1.8V/5V TSMC 180nmBCD
- Supports high temperature and long retention life time for severe automotive requirement
- Low power in Program/Erase operation for power critical applications
- Requires few (2~3) additional masks
- No change to SPICE model of Standard CMOS process, for re-using existing design and IP
-
Ultra Low Power Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
-
Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
-
Ultra Low Power Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
-
Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
-
Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
-
eTCAM (Embedded Ternary Content Addressable Memory IP
- One cycle operation latency (without priority encoder)
- Valid Bit per entry to reduce power
- Valid Bit reset in one cycle support
- Mask input option for bit-write and masked search key
-
eTCAM (Embedded Ternary Content Addressable Memory IP
- One cycle operation latency (without priority encoder)
- Valid Bit per entry to reduce power
- Valid Bit reset in one cycle support
-
sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- Foundry sponsored - sROMet compiler - TSMC 55 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
-
Memory Compilers
- Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.