LVDS IP for Tower
Welcome to the ultimate LVDS IP for Tower hub! Explore our vast directory of LVDS IP for Tower
All offers in
LVDS IP
for Tower
Filter
Compare
7
LVDS IP
for Tower
from 3 vendors
(1
-
7)
-
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
-
666 Mbps LVDS Transceiver IP
- 666 Mbps operation per channel
- Low power dissipation
- No external components
- Integrated termination resistors in transmitter and receiver.
-
LVDS transmitter - TowerJazz 0.13um
- Area: 0.015mm2
- Power: 10.9mW
- Speed: 500MS/s
- Supply: 3.3V
-
LVDS receiver - TowerJazz 0.13um
- Area: 0.008mm2
- Power: 0.66mW
- Speed: 500MS/s
- Supply: 3.3V
-
LVDS reference - TowerJazz 0.13um
- Area: 0.034mm2
- Power: 0.87mW
- Speed: 0MS/s
- Supply: 3.3V
-
Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
-
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
- • 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
- • 30 DATA + 9 RSDS CLK channels
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.13um 1P6M generic logic process.