LVDS IP for SMIC

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Compare 32 LVDS IP for SMIC from 11 vendors (1 - 10)
  • Bi-Directional LVDS with LVCMOS
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    • Operates over 2Gbps and up to 3Gb/s in some processes
    • Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
    Block Diagram -- Bi-Directional LVDS with LVCMOS
  • LVDS Receiver PHY
    • Converts 5-pair LVDS data stream into parallel 35 bits of CMOS data
    • Compatible with the TIA/EIA-644 LVDS standards
    • Supports up to 1.05Gbps data rate for UXGA
    • On-chip DLL requires no external component
    Block Diagram -- LVDS Receiver PHY
  • LVDS transmitter PHY
    • Silicon Proven in 22,28,55,65,130n,180n from SMIC, Global Foundries and Samsung
    • Compatible with the National DS90CF386
    • Compatible with the TIA/EIA-644 standards
    • Converts 35 bits data to 5-pair LVDS data stream
    Block Diagram -- LVDS transmitter PHY
  • 800MHz LVDS Cell Set for 180nm
    • 400MHz (800Mb DDR) operation.
    • Receive, Transmit and bias cells.
    Block Diagram -- 800MHz LVDS Cell Set for 180nm
  • V-by-One Tx IP, Silicon Proven in SMIC 40LL
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    • Built-in transmitter terminal impedance, no need for off-chip components
    Block Diagram -- V-by-One Tx IP, Silicon Proven in SMIC 40LL
  • RF Transceiver SMIC 55nm
    • 3GPP R14 NB_IOT??
    • SMIC55nm??
    • 2V ~ 3.6V????
    • ???:??10mA,??68mA@14dBm output,200mA@22dBm output,????<1uA
    Block Diagram -- RF Transceiver SMIC 55nm
  • LVDS TX+ (Transmitter) in UMC 40LP
    • Compatible with TIA/EIA-644 LVDS Standard
    • 49 Mbps - 770 Mbps bandwidth/channel
    • Up to 3.08 Gbps data throughput
    Block Diagram -- LVDS TX+ (Transmitter) in UMC 40LP
  • LVDS Receiver
    • Wide frequency range:
    • Power-Down Mode
    • Supports VGA, SVGA, XGA, SXGA, SXGA+ and QXGA
    • Up to 10.5 Gbit/s bandwidth
    Block Diagram -- LVDS Receiver
  • LVDS Transmitter
    • Wide frequency range:
    • Power-Down Mode
    • Supports VGA, SVGA, XGA, SXGA, SXGA+ and QXGA
    • On-chip Input Jitter Filtering
    Block Diagram -- LVDS Transmitter
  • 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
    • 25-180 MHz clock support
    • Up to 1.25 Gbps bandwidth
    • Up to 5.0 Gbps data throughput
    • Full Low power CMOS design
    Block Diagram -- 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
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