LVDS IP for GLOBALFOUNDRIES

Compare 30 LVDS IP for GLOBALFOUNDRIES from 10 vendors (1 - 10)

Bi-Directional LVDS with LVCMOS
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
LVDS RX & TX IOs in multiple foundry technology
- LVDS TX
- LVDS RX
A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF
- GPIO:
- LVDS TX & RX
- ANALOG / RF
- Physical Attributes
LVDS IO Pad Set
- Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
- Operates up to 1.2GHz (2.4Gbps)
- Input receive sensitivity of 75mV peak differential (without hysteresis)
- Common mode range from 0V to 2.4V (limited by Power Supply)
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
- LVDS compliant Tx
- 4 groups of 4-Data
- 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
- Differential polarity can be flip per lane
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
- LVDS compliant Tx
- 4 groups of 4-Data
- 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
- Differential polarity can be flip per lane
LVDS TX+ (Transmitter) in UMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 49 Mbps - 770 Mbps bandwidth/channel
- Up to 3.08 Gbps data throughput
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design