UCIe Die-to-Die Controller IP

Overview

GammaCORE UCIe D2D Controller IP enables multi-die applications, such as the connection of I/O chiplets to a main die, accelerator die to a processor die, multi-die packet processors, multi-die Ethernet switches, etc. ​

GammaCORE Controller IP core consists of the Streaming Protocol Layer, to extend the SoC interface across the UCIe link, and the Adapter Layer, to provide a reliable end-to-end link. ​

On the UCIe link side, GammaCORE provides seamless connection to the AresCORE UCIe D2D PHY IP through the RDI interface. On the system side, GammaCORE connects to one or multiple internal SoC interfaces.​

Key Features

  • GammaCORE supports ​
    • Any specific SOC Interface:  AXI4, AXI-S, TileLink, CXS, CHI, and some proprietary interfaces over UCIe. ​
    • Flit and Raw mode operation.​
    • Configurable datapath width to address specific Bandwidth and target clock frequency requirements.​
    • Combination with other Alphawave Semi companion IP cores to enable many different configurations.
  • The GammeCORE Controller IP has been verified against leading UCIe Verification IPs (VIP). The IP is silicon-proven, together with the AresCORE UCIe D2D PHY, on variety of test chips in leading-edge foundries across multiple technology nodes.

Benefits

  • High Configurability and Customizability
  • Comprehensive Verification

Block Diagram

UCIe Die-to-Die Controller IP Block Diagram

Applications

  • AI accelerators
  • Server class CPUs
  • Network switches designed for large compute
  • FPGAs
  • 5G base stations
  • IO and optical transceivers

Technical Specifications

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Semiconductor IP