The S5 Series offers 64-bit RISC-V performance with 32-bit power and area
Overview
The S5 Series offers 64-bit RISC-V performance with 32-bit power and area. The S5 core has a 5-6 stage pipeline, offering a great balance between performance and efficiency.
Key Features
- Up to 8 coherent S5 Cores and optional L2 Cache Controller
- Configurable core performance
- Double precision Floating Point Unit
- Level 1 Memory System and ECC
- Number, type, and width of bus interfaces
- Support for SiFive Insight Advanced Trace and Debug
Applications
- Consumer Electronics
- Motor Control
- Industrial Automation
- Storage
- High-performance embedded
Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Technical Specifications
Maturity
Now
Related IPs
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- Compact and Performance Efficiency 32-bit RISC-V Core
- ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
- Highest code density, Low Power 32-bit Processor with optional DSP
- Binary-compatible with the industry standard 68000 32-bit microprocessor
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.