64-bit embedded processor, fully compliant with the RISC-V ISA

Overview

SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA. An extremely small-footprint, low-power design makes the E51 Coreplex ideal for devices that require a tiny system controller for housekeeping, security, or host processing within a larger 64-bit SoC. An extended memory map of 40 physical address bits also makes the E51 Coreplex a great solution for SSD controllers and networking applications.

Key Features

Fully compliant with the RISC-V ISA specification
RV64IMAC Support:

RV64I – 64-bit RISC-V with 32 integer registers
Integer Multiplication and Division (M) support
Atomic Mode (A) support for high-performance, portable software
Compressed Mode (C) support for better code density

Machine and User Mode Support
In-order, 5-6 stage variable pipeline
Advanced Memory Subsystem:

16KB, 2-way Instruction Cache
Instruction Tightly Integrated Memory (ITIM) option
Up to 64KB Data Tightly Integrated Memory (DTIM) support

Support for up to 40 physical address bits
Efficient and Flexible Interrupts: Local interrupts w/ vectored addresses — up to 16

Platform Level Interrupt Controller (PLIC) — 511 interrupts w/ 7 priority levels
Coreplex Local Interrupts (CLINT) — 1 timer, 1 SW

8-Region Physical Memory Protection (PMP)
1.8 DMIPS/MHz
2.76 Coremark/MHz

Benefits

RV64IAC M + U Modes
Up to 1.5 GHz in 28nm
1.8 DMIPS/MHz
Physical Memory Protection (PMP)
16KB Instruction Cache
Instruction Tightly Integrated Memory (ITIM) up to 8KB
Data Tightly Integrated Memory (DTIM) up to 64KB
31 Usable Registers
511 Global Interrupts + 16 Local Vectored Interrupts
No royalties
7-page contract
Open access to all

Block Diagram

Deliverables

E51 Coreplex IP in Verilog
Constraints File (SDC)
Integration Guide covering:

Synthesis
Place and Route
Floorplanning

Test simulation environment

Technical Specifications

Availability

Now

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