SSRAM Memory Model

Overview

Key Features

• Supports SSRAM memory devices from all leading vendors.
• Supports 100% of SSRAM protocol standard of SSRAM specifications.
• Supports all the SSRAM commands as per the specs.
• Supports Continuous Data Transfer (CDT) architecture.
• Supports up to 250MHz.
• Supports following burst type
• Linear
• Interleave
• Supports separate address strobes.
• Supports synchronous self timed writes.
• Supports asynchronous output enable.
• Supports single cycle chip select.
• Supports burst read access.
• Supports burst write access.
• Supports READY status.
• Supports byte write enables.
• Supports "ZZ" sleep mode operation for partial power down.
• Supports "SHUTDOWN" mode operation for deep power-down.
• Checks for following
• Check-points include power up initialization and power off rules.
• Read/Write Command rules etc.
• All timing violations.
• Supports for full-timing as well as behavioral versions in one model.
• Supports for all timing delay ranges in one model: min, typical and max.
• Protocol checker fully compliant with SSRAM Specification.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Constantly monitors SSRAM behavior during simulation.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

Benefits

• Faster testbench development and more complete verification of SSRAM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

Block Diagram

Deliverables

• Complete regression suite containing all the SSRAM testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

Technical Specifications