IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus

SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus

Overview

The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.

The DB-SPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.

The DB-SPI-MS targets ASIC / ASSP / FPGA integrated circuits, where typically, the microprocessor is an ARM processor, but can be any embedded processor. Figure 1 depicts the system view of the DB-SPI-MS Controller IP Core embedded within an integrated circuit device.

Key Features

  • Master and Slave SPI Modes
  • Half Duplex / Full Duplex Transfers – Simultaneous Transmit & Receive
  • Original 4 Signal Interface (1 data lane, 4-wire Interface):
    • MOSI - Master Output, Slave Input (Data)
    • MISO - Master Input, Slave Output (Data)
    • SCK - Serial Clock
    • SS[N:0] - Slave Select
  • Configurable SPI Modes (Optional):
    • Standard SPI Mode (1 Data Lane)
    • Dual SPI Mode (2 Data lanes)
    • Quad SPI Mode
    • Octal SPI Mode (4 Data Lanes)(8 Data Lanes)
  • 3-wire SPI Interface (Optional)
  • Up to N=8 Slave Select (SS) Outputs for multiple Slaves on SPI Bus
  • Programmable SPI Frame Formats:
    • Programmable Words-Per-Frame
    • Programmable LSB-first or MSB-first frames
  • Two Clock Domains:
    • AMBA Bus / SCK Clocks
  • SCK Clock Generator - Master Mode (Optional):
    • Programmable SCK Rate
    • Programmable Clock Phase & Polarity
  • Configurable FIFO depth for off-loading the SPI transfers from the processor:
    • Separate Transmit / Receive FIFOs
    • Dual Clock Domains
  • DMA Controller for transfers between User Memory & SPI Bus (Optional)
  • Internal interrupts with masking control
  • Available AMBA Microprocessor Interfaces:
    • AXI / AHB / APB Buses
    • 8- or 32-bit Data Interface
  • Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
  • Fully-synchronous, synthesizable Verilog RTL core, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Benefits

  • The DB-SPI-MS-AHB Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most SPI controllers require high processor interaction involvement, the DB-SPI-MS-AHB contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the SPI transfer to the DB-SPI-MS-AHB Controller. Thus, while the DB-SPI-MS-AHB is busy, independently controlling the SPI Transmit or Receive transaction of data, the processor can go off and complete other tasks.

Block Diagram

SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus Block Diagram

Deliverables

  • Verilog or VHDL RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC
Maturity
Successful in Customer Implementations
Availability
Immediately
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